SPI Enabled 64x8 SRAM Memory Design for Biomedical Applications

Abstract

In this paper, a Static Random Access Memory (SRAM) architecture with a 512-bit RAM is implemented, and verified together with a Serial Peripheral Interface (SPI) protocol. The design was realised using Cadence Virtuoso EDA tools of schematic capture, simulation, layout validation and carried out using 180 nm CMOS technology. The improved architecture employs a popular industry standard of serial communication, the SPI to coordinate memory access, such as read, write and control, as opposed to standard parallel SRAM modules. The architecture is a compact and energy-efficient memory system as SPI reduces the amount of pins significantly, interconnect complexity, and overall power consumption of 1.34 mW with a power-delay product (PDP) of 24.1 pJ. The design has been specifically optimized to suit the requirements of low-power applications with moderate access rates with low energy usage. Specifically, such a memory design can be applied to IoTbased environmental sensors, wearable computers, and batteryoperated embedded systems, in which energy efficiency is more important than high-speed access to data. Functional verification establishes the stability of the SRAM to the constraints of the SPI protocol, enabling the successful completion of all memory operations without any failure in the conditions of varying process variations in the 180nm CMOS. SPI-based interfacing of the microcontroller (MCU) not only eases microcontroller interfacing but also enables scalability to memory sizes that are larger, is a solid foundation for future developments of energyconscious battery-operated applications. © 2026 IEEE.