Embedding Steganography Digest Using Shannon's Decomposition for Hardware Security Against False IP Ownership Attack

Abstract

High level synthesis (HLS) framework is widely used in designing hardware accelerators as a dedicated reusable intellectual property (IP) core. However, the inclusion of multiple entities in the global design supply chain process has injected security vulnerabilities, which therefore mandates to secure hardware IP cores against threats such as IP piracy and false IP ownership claim. This paper presents a novel security methodology that exploits encoded steganographic digest using Shannon's decomposition to embed security constraints at the gate-level of the hardware IP. This includes generation of encoded steganographic digest, which is subsequently embedded into the IP design. The proposed approach is capable to provide detective control against piracy, and false IP ownership claim with the help of implanted digital evidence in the HLS generated IP design. The proposed approach achieves lower probability of coincidence and higher tamper tolerance, as well as enhanced entropy than prior approaches (7.65 E+98 times better) at negligible design overhead. � 2025 IEEE.