T-HAC: Time-Sensitive HLS Trojan Attack for Affecting Controller Timing Signal of Hardware IP Designs

Abstract

High level synthesis (HLS) is a de-facto standard for designing hardware intellectual property (IP) designs. However, recent research has shown security vulnerabilities (in the form of backdoor hardware Trojan) that may exist during different stages of HLS tool development process. This paper presents a new class of HLS-aided Trojan attack called T-HAC: Time-sensitive HLS Trojan Attack for affecting Controller timing signal of hardware IP designs. It can be automatically injected/embedded in a stealthy manner by an adversary/attacker during HLS datapath designing stage (of tool development process) at the interface between controller and datapath of the IP design. Results of the proposed T-HAC HT yielded significant timing signal delay (degradation) achieved, at nominal design area/power overhead. � 2009-2012 IEEE.