Towards Improved Performance Metrics for Karatsuba Multiplier and Number Theoretic Transform (NTT)-Based Polynomial Arithmetic Multiplier for PQC Primitives

Abstract

Integer polynomial multiplication using number theoretic transform (NTT) poses a performance challenge in terms of computation time and power in post-quantum cryptography (PQC)-driven applications. PQC implementations require efficient arithmetic operations, especially for lattice-based cryptographic schemes. Polynomial multiplication based on Number-Theoretic Transform (NTT) provides many more computational advantages due to its convolution operations. In this paper, we explore Number-Theoretic Transform (NTT)-based polynomial arithmetic multiplier for 8-bit, 16-bit, 32-bit, and 64-bit integers. In addition, we perform a comparative assessment of the Number-Theoretic Transform (NTT)-based multiplication technique and the Karatsuba multiplication method for inputs of equal size. The goal is to assess the hardware trade-offs across the architectural implementations in the usage of DSP blocks, LUT slices, maximum delay, and power consumption to guide hardware design decisions for Post-quantum cryptography (PQC) implementations on an FPGA platform. These findings present a comprehensive analysis of how each multiplication method adapts to various architectural limitations and input sizes. The NTT-based polynomial arithmetic multiplier consumes the highest total logic power of 26.16 W for 64-bit operand width, whereas the DSP-based non-recursive Karatsuba multiplier consumes the least total logic power of 4. 5 9 W for 64-bit operand width. � 2025 IEEE.