ULTRA-MACE: A Unified Low-bit Trans-precision Reconfigurable Multiply-Accumulate Compute Engine for Accelerated Computing

Abstract

The rising demand for energy- and resource-efficient edge-AI platforms calls for compute engines that balance throughput, flexibility, and run-time efficiency under tight bandwidth constraints. This brief presents ULTRA-MACE, a unified low-bit trans-precision reconfigurable multiply-accumulate compute engine (MACE) that supports FP4 (E2M1), FP8 (E4M3), Posit-(8,2), and Posit-(16,3) through a six-stage vectorized pipeline with 128-bit quire accumulation. ULTRA-MACE employs a high-precision split mantissa multiplication scheme and an integrated gated bypass for ReLU, achieving 4�/2�/2�/1� throughput (FP4/FP8/Posit-8/Posit-16) without increasing bandwidth demand. Post-route results in 28nm CMOS demonstrate a peak energy efficiency of 12.8 TFLOPS/W at 0.9 V and a compute density of 8.2 TFLOPS/mm2. Integrated into the TREA accelerator with 64 MACE, the FPGA prototype achieves 89% of theoretical peak performance and maintains practical accuracy with only 1.5% degradation relative to the FP32 baseline. Overall, these results demonstrate an efficient trans-precision compute engine for edge-AI acceleration. � 1982-2012 IEEE.