Hybrid Memristor-Based Logic Gates (HMBLG) for Energy-Efficient and High-Speed Digital Circuits with Practical Implementation NOT and OR

Abstract

The conventional CMOS-based logic faces increasing power consumption and component-density problems which limit further scaling. Although some memristor-based logic (IMPLY, MAGIC, MRL) can reduce some overheads, it often introduces signal degradation, complexity, or slower operation. To overcome these challenges, we introduce new Hybrid Memristor-Based Logic Gates (HMBLG), which combine memristive elements with CMOS transistor. All logic gates were designed used a nonlinear analytical memristor model and implemented in Verilog-A within Cadence Virtuoso. All simulations were performed using a 180nm CMOS technology library. These simulation results show HMBLG is significantly outperforming both CMOS-based and previous reported memristor logic. The NOT gate power reduces from 129.9 μW to 0.2247 μW, and OR gate delay falls from 10119 ps to 0.01 ps. Comparable increases are observed for AND, NOR, NAND, XOR, and XNOR. Moreover practically demonstrated NOT and OR gates used Y2O3 memristor crossbar array. These results provide that HMBLG has low power, reduced delay, and fewer components. © 2026 IEEE.