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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Nirala, Rohit Kumar | en_US |
| dc.contributor.author | Kranti, Abhinav | en_US |
| dc.date.accessioned | 2026-07-09T06:48:16Z | - |
| dc.date.available | 2026-07-09T06:48:16Z | - |
| dc.date.issued | 2026 | - |
| dc.identifier.citation | Samant, N., Agavekar, A. A., Ganesh, D., Nirala, R. K., Gupta, M., & Kranti, A. (2026). Enabling Logic-in-Memory (LiM) Functionality with Junctionless FeFETs. 2026 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2026 - Proceedings of Technical Papers. https://doi.org/10.1109/VLSITSA69131.2026.11527893 | en_US |
| dc.identifier.isbn | 979-833156238-0 | - |
| dc.identifier.other | EID(2-s2.0-105041905149) | - |
| dc.identifier.uri | https://dx.doi.org/10.1109/VLSITSA69131.2026.11527893 | - |
| dc.identifier.uri | https://dspace.iiti.ac.in:8080/jspui/handle/123456789/18677 | - |
| dc.description.abstract | Implementing logic (NOR/NAND) by utilizing the polarization of HZO ferroelectric (Fe) layer in field effect transistors (FETs) opens new possibilities for realizing logic operations within memory. Despite the relatively simpler fabrication process, junctionless (JL) Fe FETs exhibit a degraded State 1 and are unsuitable for implementing logic-in-memory (LiM). The drawback is addressed through a co-optimization of channel doping (1018 cm-3 instead of 1019 cm-3) and gate workfunction (midgap 4.7 eV rather than 5 eV) which enables NOR/NAND operations in JL FeFETs and their adaptation in LiM modules. © 2026 IEEE. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_US |
| dc.source | 2026 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2026 - Proceedings of Technical Papers | en_US |
| dc.title | Enabling Logic-in-Memory (LiM) Functionality with Junctionless FeFETs | en_US |
| dc.type | Conference Paper | en_US |
| Appears in Collections: | Department of Electrical Engineering | |
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