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| Title: | HLS Driven Obfuscation of DSP Hardware IP Designs using Non-invertible Arbitrary Function and Reconfigurable Intertwined Obfuscation Logic |
| Authors: | Sengupta, Anirban Bhui, Nabendu Chourasia, Vishal Singh, Ayush Kumar |
| Issue Date: | 2026 |
| Publisher: | Institute of Electrical and Electronics Engineers Inc. |
| Citation: | Sengupta, A., Bhui, N., Chourasia, V., & Singh, A. K. (2026). HLS Driven Obfuscation of DSP Hardware IP Designs using Non-invertible Arbitrary Function and Reconfigurable Intertwined Obfuscation Logic. 2026 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2026 - Proceedings of Technical Papers. https://doi.org/10.1109/VLSITSA69131.2026.11527771 |
| Abstract: | Digital Signal Processing (DSP) hardware intellectual property (IP) designs are pivotal to the proliferation of consumer electronics (CE) systems such as camera, camcorder, smart watch, smart TVs, IoT etc. Such DSP hardware IPs is typically designed using high level synthesis (HLS) framework. However, with the globalization of integrated circuit/system-on-chip (SoC) design supply chain, emergence of threats such as reverse engineering (RE) has become a matter of grave concern. This paper presents novel HLS-driven functional obfuscation of DSP hardware IP designs using non-invertible arbitrary function and reconfigurable intertwined obfuscation logic. The proposed approach thwarts RE attack by hindering various forms of threats such as key-sensitization attack, removal attack, different versions of SAT attack and ML attack. Results of the proposed approach revealed significantly greater obfuscation strength (causing reduced probability of attacks) than prior approaches. © 2026 IEEE. |
| URI: | https://dx.doi.org/10.1109/VLSITSA69131.2026.11527771 https://dspace.iiti.ac.in:8080/jspui/handle/123456789/18684 |
| ISBN: | 979-833156238-0 |
| Type of Material: | Conference Paper |
| Appears in Collections: | Department of Computer Science and Engineering |
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