HierCIM: A 16-Kb SRAM-Based Digital CIM Macro With Hierarchical Adder-Tree Accumulation for Edge CNN Inference

Abstract

The growing demand for efficient deep-learning inference on edge platforms requires hardware that is both energy-efficient and practically implementable. This work presents a 16-Kb all-digital static random-access memory (SRAM)-based compute-in-memory (CIM) macro for low-bit CNN inference, featuring a hierarchical adder-tree-based accumulation architecture. The design integrates a nor-enabled SRAM compute cell, column-wise rearrangement network, sparsity-aware compression, and multistage hierarchical accumulation within a 64-bank 64 × 4 architecture, enabling scalable bit-serial processing and utilization-aware mapping. Implemented in 65-nm CMOS, the macro achieves 8.19 TOPS effective throughput at 1.0 V and a peak energy efficiency of 586 TOPS/W at 0.9 V under practical operating conditions. Hardware-compatible CNN mapping is demonstrated using LeNet-5, VGG-8, and ResNet-8. The design achieves 98.1% and 72.3% accuracy on MNIST and CIFAR-10, respectively, with 1-bit activations and 4-bit weights, while 4-bit configurations on deeper networks show only 3%–4% degradation from FP32 baselines. CNN inference is evaluated using a hardware-compatible post-training quantization (PTQ) flow without retraining. These results demonstrate that the proposed SRAM-CIM architecture provides an efficient and scalable accumulation solution with a practical tradeoff among throughput, energy efficiency, and implementability for edge-oriented deep neural network (DNN) inference. © 1993-2012 IEEE.