HLS Register Allocation Attack for Compromising Hardware IP Designs using HLS-aided Trojan

Abstract

High Level Synthesis (HLS) has emerged as an industry de-facto standard in designing hardware accelerators and reusable intellectual property (IP) cores used in the system-on-chips (SoCs). However, the design process of HLS exposes critical security vulnerabilities in the form of backdoor hardware Trojan (HT). This paper presents a novel HLS-aided Trojan for register allocation tampering (RAT) attack, without affecting the functionality of the IP design. It introduces a new variant of HLS Trojan called ‘RAT-HT’ that can be secretly inserted by an HLS tool developer during datapath design stage for tampering register allocation information, also resulting into unwarranted power drainage. The proposed timer-sensitive HLS-aided RAT-HT attack is capable of inducing tampered register allocation as well as greater power drainage than prior works. © 2013 IEEE.