BE-IMC: Bit-interleave 8T SRAM based In-Memory Computing macro for AI edge devices

Abstract

In-Memory Computing (IMC) is a new paradigm to improve energy efficiency and throughput for Artificial Intelligence (AI) edge devices. In this paper, Shared Pass-Gate Bit-interleave (SPGB) Enable 8T SRAM-based IMC (BE-IMC) macro is proposed for energy-efficient in-memory computations. The proposed BE-IMC macro uses the shared pass gate write scheme to incorporate a bit-interleave structure and address the half-select problem. Further, an Input-Boost Voltage Sense Amplifier (IB-VSA) is proposed to improve the input margin by 2.57× when compared to conventional voltage SA. A 16-Kb SRAM array-based IMC macro is implemented in a 65-nm node and achieves an energy efficiency of 1502 TOPS/W at 24MHz clock frequency and a supply voltage (VDDmin) of 0.32 V. The proposed BE-IMC macro achieves an array efficiency of 80.9% for a 128 × 128 SPGB-8T SRAM array, including all peripherals such as column-wise proposed IB-VSA and decoder and drivers. Further, the 2-layer Multi-Layer Perceptron (MLP) neural network is implemented by integrating the proposed BE-IMC macro and IB-VSA parameters in the modified MLP+Neurosim framework. The 2-layer MLP neural network implementation achieves the online learning (hardware learning and hardware classification) and offline learning (Software learning and hardware classification) accuracy of 95.48% and 97.04%, respectively on the MNIST dataset. © 2026