Resource-Efficient Linear Decomposition of n-Input Majority Using Folded-bias Carry-Save Addition

Abstract

Efficient decomposition of high-fan-in majority functions is important for logic synthesis and technology mapping. The expanded Hamming-weight-plus-threshold (HW+TH) baseline computes a Hamming-weight representation and then applies a separate threshold-add stage. This paper proposes a folded-bias carry-save addition (CSA) approach for decomposing odd n-input majority functions. For the majority threshold Tn = ⌈n/2⌉, the method selects w = ⌈log2(Tn)⌉ and folds the constant K = 2w − Tn into the CSA columns. The majority decision is obtained directly as the carry into column w, eliminating the separate threshold-add stage without materializing a standalone Hamming-weight word. The construction is proved correct and has linear structural size, while its depth and mapped delay are evaluated empirically. The proposed method is evaluated using generator-level arithmetic metrics, pre-mapping structural metrics, logic-synthesis flows, and FPGA implementation. For n ∈ {5, 7,..., 61}, it reduces the mean full-adder count by 28.73% and the mean initial k-LUT node count by 26.02% relative to the expanded HW+TH baseline. After light MIG optimization, the mean node count decreases by 5.07%. Under a common strong ABC+LUT6 flow, the mean LUT6 count decreases by 1.76%. Vivado synthesis on Artix-7 reports reductions of 4.46% in mean CLB-LUT count and 0.34% in mean datapath delay. Under a common two-input AIG normalization, Fiction QCA-ONE layouts reduce cell-layout footprint by 6.74%, quantum-dot cellular automata (QCA) cell count by 14.74%, and critical-path clock zones by 3.97%. These results show that folded-bias CSA reduction consistently provides a smaller structural starting network, while mapped area and delay outcomes remain target and synthesis-flow dependent. © 1982-2012 IEEE.