Ultra low power memory design for implantable pacemaker chip

Abstract

Implantable pacemakers are life-critical biomedical devices that continuously monitor cardiac activity and regulate abnormal heart rhythms through electrical stimulation. Modern pacemaker systems require reliable and low-power memory architectures for buffering and storing electrogram (EGM) signals acquired from sensing channels. Existing pacemaker architectures mainly focus on sensing, stimulation, and analog front-end circuitry, while efficient large-scale digital memory organization and low-power external memory interfacing receive limited attention. This thesis presents the design and implementation of a lowpower SPI-enabled SRAM architecture for implantable pacemaker applications. The proposed architecture integrates a Serial Peripheral Interface (SPI) communication protocol with a banking-based SRAM organization to support efficient external memory access and EGM signal buffering. An 8192→8 single-port SRAMmacro is implemented as the basic memory block, and eight SRAM macros are integrated to construct a 64 KB memory system using address partitioning and decoder-based bank selection. The complete RTL-to-GDSII implementation flow is carried out using Cadence EDA tools in SCL 180 nm CMOS technology including synthesis, floorplanning, placement, CTS, routing, and physical verification. The final implementation achieves a maximum operating frequency of 48.95 MHz with total power consumption of approximately 2 mW. The proposed SPI-enabled SRAM architecture demonstrates an efficient and scalable low-power memory solution suitable for implantable biomedical systems requiring continuous biomedical signal bu!ering.