Power analysis and feedback to optimize power of mixed signal SoC’s

Abstract

With technology scaling and an increase of chip complexity, the power consumption of chip has been rising and its power architecture is getting complicated. Many power management techniques like power gating, multi-voltage, multi-threshold are applied to reduce the power dissipation of devices. UPF is an IEEE 1801 standard format to describe the power architecture, also called power intent, including power network connectivity and power reduction methods. It enables verification of power intent in the early phases of the design cycle. The UPF developed should be consistent with the design at all stages of the design cycle and it should be updated according to the modifications made in the design. In Normal Synthesis Flow we there are no power efficient techniques involved so we go with modified synthesis flow to reduce the power w.r.t to power reduction techniques discussed in the thesis. Normal synthesis flow doesn’t give the flexibility with power whereas if we go with the Modified Synthesis flow not only we can effectively manage to reduce power but we can also see the effective utilization of power and wastage. Besides, parallel development of power intent for complex designs, limitations of UPF standard to describe few power intent components effectively and time-consuming conventional UPF flow hinder efficient UPF development and management problems and some of its solutions are discussed. This methodology also ensures proper restructuring and demotion of UPF along with automation of UPF development, demotion, and verification. This methodology is applied to a design consisting of memory and basic modules and we can say that the flow discussed above has effectively reduced power up to 28% at the RTL stage itself and has been further optimized while doing the physical implementation.