Reliable functionality verification system for MIPI CSI-2 (camera serial interface)

Abstract

MIPI CSI-2 became popular in the mobile industry for interfacing camera and other host devices, e.g. mobile processor because of its ease of use, high performance, and its ability to support high-resolution photographic images and videos. However, with the increasing requirement of the amount of data stored in one image and thus resulting in high power and the need of transmitting a huge amount of data, it became important to have a fresh perspective. So, we implemented some new techniques, i.e. introducing C-PHY as an alternative PHY layer, using LRTE EPD for packet spacing, and introducing SROI to improve data rate, power, and reducing the amount of data. As a result, replacement of D-PHY with CPHY layer improves data rate and power, using LRTE EPD for packet spacing reduces latency and improves transmission efficiency and SROI provides a method to transmit only regions of interest thus reducing the amount of data transferred, which results in high frame rate and low power dissipation. However, implementing new features in a protocol requires tracking of human errors and bugs introduced in the system, which may result in unpredictable behavior of design which is done through implementing tests in a verification system. Manual tracking of failure or success of tests is difficult and is not very accurate, and hence it became imperative to design an automatic system for keeping track of bugs and total features tested. So, a new verification architecture is proposed, which contains a scoreboard and coverage class, improving the accuracy and efficiency of design.