Automated verification of extracted timing models

Abstract

IC design process consist of many steps other than designing such as logic synthesis, functional verification, placement, routing, etc before the design can be sent for fabrication. Static Timing Analysis (STA) plays a vital role in today’s designing of commercial circuits. It needs to be performed repeatedly after multiple steps of IC design process. STA ensures that the chip being designed meets timing requirements. Static timing analysis is a method of figuring the expected timing of a digital circuit without demanding simulation of the full circuit. Most commercial chip designing and implementation of IP models use Extracted Timing Models (ETMs) for faster overall process. Extracted Timing Models were created after performing Static Timing Analysis in this work. These models also need to be verified after their creation. These timing models are usually verified manually. This manual verification is very slow. To speed this up, Automated Verification of Extracted Timing Models is done in this work. This has found too significantly reduce the time of Verification of Extracted Timing Models. The circuits designed for testing the ETM Verification method are Approximate MAC unit and a Memory Controller. MAC Units find vast applications in computing from Arithmetic Logic Units (ALUs) to Artificial Neural Networks. Approximate MAC Unit designed here is a MAC Unit with some approximations for faster working using less number of gates. Another circuit designed for ETM Verification is a memory controller. A Memory Controller is a digital circuit that manages the movement of data to and from a memory. Designing semiconductor memories focuses on correct functionality of the circuit, make the most of circuit density, and engaging circuits such that clock and data signals are efficiently routed. These commercial semiconductor memories used today need many essential circuits to function properly like Memory Controllers. Memory Controller was designed using Verilog HDL during this work.