Designing of low power high speed current mode logic serdes

Abstract

Transmission of data from a source to destination with error protection is the main aim of communication. Communication can be established in a parallel way or serial way. In parallel communication each bit of data require a separate line for transmission. But as according to the Moore’s Law number of transistor density in increasing resulting in the growth of pin interconnect density. Thus the unrivaled solution is to use SerDes. SerDes uses serial communication for data transfer. The SerDes is used not only in backplane drivers but also in high speed IO interface such as chip-to-chip, chip-to-backplane and chip-to-memory. SerDes is becoming a common building block for ASICs. SerDes will become pervasive IO solution but also the characteristic and optimization of these links present new challenges. With the increase in speed of communication and complexity of circuits more fast and compact SerDes are required. SerDes itself have its design concerns such as error correction, load matching at the receiver, area constants, speed and power consumption. In this work, our main aim is to reduce the power with optimal speed. Current Mode Logic is used because it has a power advantage over CMOS at high speed. It has great error immunity as compared to conventional methods. Our work is divided in two parts. First to design a synchronous SerDes. Synchronous SerDes is designed using CML mux. A new parallel chain method is used at deserializer. This all help us to reach a speed of 16:64Gbps speed with only 9:29mW. In second work, we designed a asynchronous SerDes, which was designed with the help of CML latch. Asynchronous since does not require clock, saves lot of power from PLLs and CDRs. The asynchronous circuit operates at 18:92Gbps consuming only 8:82mW power.