Low cost fault reliability and trojan security aware high level synthesis for application specific datapath processors

Abstract

With changing trends in technology and to effectively compete in the market, designers are focussing on attempts to optimize Very Large Scale Integration (VLSI) digital systems. Attempts to devise design systems with higher performance, accuracy and efficiency along with lower overall cost are being made. In order to achieve this, High Level Synthesis (HLS) / architectural synthesis has come into force. However, there is a paradigm shift in the area of HLS as more and more designs are suffering from reliability and hardware security issues. These are expected to become the key focus due to massive scaling in nanometre technology and globalization involved in the VLSI design process. This thesis proposes methodologies for generating low cost security solutions for both transient fault and hardware Trojan with respect to data intensive and control intensive applications during design of application specific datapath processor at behavioural level. This thesis solves five different types of problems in generating reliable//hardware secured designs: a) Problem of design Space Exploration (DSE) during power-performance trade-off for data intensive applications that produces high quality design solutions. In addition, a novel Bacterial Foraging Optimization (BFO) driven DSE methodology is proposed which explores the design points in the design space. A novel chemotaxis, replication and elimination-dispersal algorithm is proposed which generates the design points. b) Problem of exploration of low cost optimal k-cycle transient fault secured datapath during power-performance trade-off for data intensive applications. A novel fault security algorithm for handling single and multi-cycle transient faults is proposed. A novel multi-cycle Single Event Transient (SET) fault security aware multi objective DSE methodology that explores an optimal combination of transient fault secured (Double Modular Redundant) DMR datapath configuration has been proposed. Moreover, a novel scheme for selecting appropriate edges for inserting cuts in the scheduled Data Flow Graphs (DFG) minimizing delay overhead associated with transient fault security, a novel execution time model for estimating the execution time of a transient fault secured/Trojan secured design during DSE process, a novel fitness function, used for design quality assessment in DSE process has been proposed. c) Problem of exploration of low cost optimal k-cycle transient fault secured datapath during area-delay trade-off for control intensive applications. a novel multi-cycle SET fault security aware multi objective DSE methodology that exploresan optimal combination of transient fault secured DMR datapath configuration and loop Unrolling Factor (UF) for Control Data Flow Graphs (CDFG) has been proposed. Moreover, a novel estimation model for computation of execution delay of a loop unrolled CDFG (based on a resource configuration explored) without tediously unrolling the entire CDFG for the specified loop value has been proposed. d) Problem of exploration of low cost optimal kcycle transient fault tolerant datapath based on power-performance tradeoff for data intensive applications. In relation to this, a novel multi-cycle transient fault tolerant algorithm that has capability to isolate original and duplicate units in a DMR with respect to the transient fault has been proposed. Moreover, a novel equivalent circuit that works with DMR systems performs the function of extracting the correct output from the DMR design has been proposed. e) Problem of exploration of low cost optimal Trojan secured datapath during behavioural synthesis for data intensive applications has been tackled. A novel encoding scheme for representing bacterium in the design space (comprising of candidate datapath resource configuration and vendor allocation information for hardware Trojan secured datapath) has been proposed. Moreover, a novel exploration process of anefficient vendor allocation procedure that assists in yielding a low cost hardware Trojan secured datapath within user constraints has been proposed.