Hardware (IP) security for DSP and multimedia applications

Abstract

A core based design paradigm has become popular in the semiconductor business market for the last few decades. The underlying reasons are the increasing time to market pressure, design complexity and cost of system-on chip (SoC) designs. However, the contrast impact of core based design paradigm is the susceptibility of the intellectual property (IP) cores towards the hardware threats of IP piracy and hardware Trojan insertion. An adversary in the untrusted SoC design house may infringe or misuse the IP core for personal benefits. Moreover, the reliance of chip manufacturing on a distinct offshore foundry also enhances the risks of IP piracy and potential Trojan insertion. The digital signal processing (DSP) and multimedia applications are thriving in the modern consumer electronics (CE) market. The stringent performance and low power demand have enforced the realization of DSP and multimedia applications through their hardware accelerator or application specific IPs. However, owing to the proliferating usage of DSP and multimedia IPs in the SoCs, their security concerns cannot be undervalued. Hence, an IP core designer needs to employ protection measures against the piracy and potential Trojan insertion attacks to ensure trust in hardware. For highly complex designs such as DSP and multimedia cores, a high level synthesis (HLS) framework is amenable to employing security mechanisms. Towards the security of IP cores, this thesis contributes the following novel methodologies: (a) IP core steganography approaches to secure DSP cores against piracy, (b) a hologram based obfuscation approach to thwart the potential Trojan insertion attack, (c) double line of defense approaches based on structural obfuscation and IP vendor’s secret mark to counter both Trojan insertion and IP piracy attacks, (d) secured hardware accelerator design approach for various image processing filter applications and a DFT processor.