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Issue Date	Title	Author(s)
2017	Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis	Roy, Dipanjan; Sengupta, Anirban
2023	Methodology for exploration of security-design cost trade-off for signature-based security algorithms	Sengupta, Anirban; Chaurasia, Rahul
2022	IP Core Protection of Image Processing Filters with Multi-Level Encryption and Covert Steganographic Security Constraints	Anshul, Aditya; Sengupta, Anirban
2015	Design space exploration of datapath (architecture) in high-level synthesis for computation intensive applications	Sengupta, Anirban
2013	D-logic exploration: Rapid search of Pareto fronts during architectural synthesis of custom processors	Sengupta, Anirban; Mishra, Vipul Kumar
2017	DSP design protection in CE through algorithmic transformation based structural obfuscation	Sengupta, Anirban; Roy, Dipanjan
2020	Design Space Exploration of DSP Hardware Using Adaptive PSO and Bacterial Foraging for Power/Area-Delay Trade-Off	Sengupta, Anirban; Rathor, Mahendra
2018	Comprehensive operation chaining based schedule delay estimation during high level synthesis	Mishra, Vipul Kumar; Sengupta, Anirban
2014	Integrated particle swarm optimization (i-PSO): An adaptive design space exploration framework for power-performance tradeoff in architectural synthesis	Sengupta, Anirban; Mishra, Vipul Kumar
2017	A Framework for Hardware Efficient Reusable IP Core for Grayscale Image CODEC	Sengupta, Anirban; Roy, Dipanjan