Introduction: Secured and optimized hardware accelerators for DSP and image processing applications

Abstract

This chapter provides a background introduction on hardware accelerators, followed by its relevance in today’s digital world as well as the security modules/ algorithms being used to secure a hardware accelerator and finally ending with the paradigm shift needed for the future. The chapter is organized as follows: Section 1.1 discusses about the definition, significance and application of hardware accelerators, followed by the role of electronic system level (ESL) synthesis in hardware accelerator design in Section 1.2; Section 1.3 provides significant details on the popular hardware accelerators for digital signal processing (DSP) and image processing applications by including details of its mathematical function/algorithm. Section 1.4 presents a background summary of important security algorithm/modules used for securing hardware accelerators by especially giving reference to the chapters where it is discussed; Section 1.5 explains the new paradigm shift expected in future for hardware and very large scale integration (VLSI) communities; Section 1.6 concludes the chapter, while Section 1.7 provides questions and exercise for the readers. © The Institution of Engineering and Technology 2021.