Multimodal hardware accelerators for image processing filters

Abstract

The chapter describes hardware accelerators for image processing filters, including design methodology and security technique employed for the following: blur filter, sharpening filter, embossment filter and Laplace edge-detection (ED) filter. The chapter is organized as follows: Section 5.1 discusses the reasons for using dedicated image processing filter hardware, Section 5.2 discusses the motivation for designing secure image processing filter hardware accelerators, Section 5.3 presents the salient features of this chapter, Section 5.4 discusses some selected contemporary approaches, Section 5.5 discusses the theory of 3 × 3 filter hardware accelerator, Section 5.6 presents designing of functionally reconfigurable obfuscated 3 × 3 filter hardware accelerator, Section 5.7 discusses the theory of 5 × 5 filter hardware accelerator, Section 5.8 presents designing of obfuscated 5 × 5 filter hardware accelerator, Section 5.9 presents designing of secured application specific filter hardware accelerators, Section 5.10 presents the equivalent MATLAB® codes for image processing filters, Section 5.11 presents additional information on image processing convolution filters, Section 5.12 presents analysis of case studies, Section 5.13 concludes the chapter and Section 5.14 presents some questions and exercise for the readers. © The Institution of Engineering and Technology 2021.