Designing a secured N-point DFT hardware accelerator using obfuscation and steganography

Abstract

N -Point DFT is an important DSP algorithm which fmds numerous applications in electronics. A hardware accelerator design of DFT is vital to improve system performance. However, the design process of a DFT hardware accelerator poses security risks due to growing hardware threats such as Trojan insertion, false claim of ownership and piracy. This entails enabling security of DFT hardware accelerator designs, by the designer/vendor. This chapter discusses a secured design flow of N -point DFT hardware accelerator using HLS framework. The robust security of DFT hardware accelerator design has been ensured using two security mechanisms, structural obfuscation and crypto-steganography. Steganographybased security mechanism employed on the top of structural obfuscation enables detective control along with preventive control. The case study of 4 -point DFT hardware accelerator in terms of security and design cost analysis shows that robust security has been achieved at the cost of negligible design overhead. © The Institution of Engineering and Technology 2021.