Forensic detective control using hardware steganography for IP core protection

Abstract

This chapter discusses forensic detective control using hardware steganography for intellectual property (IP) cores or integrated circuits. The chapter is organized as follows: Section 2.1 introduces the utility or applications of hardware steganography; Section 2.2 discusses the threat model for which hardware steganography is applicable; Section 2.3 presents comparative study on contemporary approaches; Section 2.4 explains the IP core steganography model; Section 2.5 discusses forensic detective control using hardware steganography for digital signal processing (DSP) cores; Section 2.6 presents the design process of the hardware steganography process for DSP cores; Section 2.7 analyses security properties of hardware steganography; Section 2.8 presents an analysis and comparison of hardware steganography with watermarking for different DSP IP cores; finally, Section 2.9 concludes the chapter. © The Institution of Engineering and Technology 2020.