Multi-phase obfuscation for fault-secured DSP circuits

Abstract

This chapter discusses a multi-phase obfuscation process for fault-secured intellectual property (IP) cores during electronic system level (ESL) synthesis. A detailed elaboration on the threat model for fault-secured IP cores is followed by the use of the multi-phase obfuscation process for digital signal processing (DSP) circuits and, finally, analyses of case studies. The chapter is organized as follows: Section 7.1 discusses fault-secured IP cores and their needs, followed by different threats to fault-secured IP cores and how to solve them. Section 7.2 focuses on the differences between functional obfuscation and structural obfuscation. Section 7.3 presents the problem formulation for protecting fault-secured IP cores. Section 7.4 discusses selected contemporary structural obfuscation approaches used to date. Section 7.5 provides an overview of the multi-phase obfuscation approach followed by evaluation models used and details of the approach in the context of fault-secured DSP circuits. Section 7.6 demonstrates the multi-phase obfuscation approach on a fault-secured finite impulse response (FIR) filter. Section 7.7 presents analyses based on case studies. Section 7.8 concludes the chapter. © The Institution of Engineering and Technology 2020.