Transient fault secured/tolerant architecture for DSP core

Abstract

In this chapter we have provided a detailed description to TFs, its origin and its impact on integrated circuits. Further, we have discussed recent state-of-the-art methodologies present in the literature that provides security and/or tolerance subsequent CS doesn’t require shifting of primary outputs. Hence, overall schedule delay is not affected. Similarly, as shown in Figure 16.15, for k = 10 and k m = 4, a small increment in the delay for [4] in case of large size benchmarks is observed. However, the delay overhead is within acceptable limits. (Note: during above delay comparison the delay overhead of two CS due to comparators and voter is not considered for analysis of delay overhead. This was done to provide analysis of delay overhead resulting only due to shifting of operations during scheduling and allocation. © The Institution of Engineering and Technology 2019.