Design Pruning of DSP Kernel for Multi Objective IP Core Architecture

Abstract

Owing to significant market pressure the design and development time for the intellectual property (IP) core needs to be rapid with concurrent minimization in the cost of development. For most of the modular systems the optimization and accurate selection of the system architecture is one of the prime stages of the development process. But the process of accurate selection of the architecture by early planning and efficient design space exploration is very lengthy and expensive. Furthermore the evaluation of the design space through exhaustive search technique is strictly forbidden. Any mistake in the development process during architecture selection leads to devastating effects in system output and expenditure. Redesigning the system requires extensive hours of work for the designer and incurs high cost. In this paper we provide a novel design space exploration strategy for the design of systems based on hard real time processing and multi parametric optimization requirements. Furthermore we provide an approach which helps in rapid re-selection of the architecture when the system requires reconfiguration in architecture such as relaxation in timing constraint or changes in other objective parameters (such as hardware area). © 2019 IEEE.