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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Sengupta, Anirban | en_US |
dc.date.accessioned | 2022-03-17T01:00:00Z | - |
dc.date.accessioned | 2022-03-17T15:34:59Z | - |
dc.date.available | 2022-03-17T01:00:00Z | - |
dc.date.available | 2022-03-17T15:34:59Z | - |
dc.date.issued | 2018 | - |
dc.identifier.citation | Sengupta, A., & Mohanty, S. P. (2018). Functional obfuscation of DSP cores using robust logic locking and encryption. Paper presented at the Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, , 2018-July 709-713. doi:10.1109/ISVLSI.2018.00133 | en_US |
dc.identifier.isbn | 9781538670996 | - |
dc.identifier.issn | 2159-3469 | - |
dc.identifier.other | EID(2-s2.0-85052091582) | - |
dc.identifier.uri | https://doi.org/10.1109/ISVLSI.2018.00133 | - |
dc.identifier.uri | https://dspace.iiti.ac.in/handle/123456789/4623 | - |
dc.description.abstract | Obfuscation plays a key role in thwarting attacks launched through reverse engineering process. This work presents a new obfuscation process for DSP cores using improved logic locking and encryption that incurs minimum design overhead and achieves reduced design cost compared to state of the art approaches. The proposed approach integrates particle swarm optimization driven design space exploration system (PSO-DSE) for obtaining reduced design cost of obfuscated DSP designs. Enhanced security of locking is provided through locking blocks that are capable of locking each output data bit of functional resources with 8 key bits. The presented approach includes countermeasures against key sensitization attacks, SAT attacks and removal attacks. Results indicate that the proposed approach has been capable of achieving enhanced obfuscation security by at least 4.29 e+9 times and a design cost reduction ~ 6.5 % compared to a recent approach. © 2018 IEEE. | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE Computer Society | en_US |
dc.source | Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI | en_US |
dc.subject | Computer circuits | en_US |
dc.subject | Cost reduction | en_US |
dc.subject | Cryptography | en_US |
dc.subject | Digital signal processing | en_US |
dc.subject | Keys (for locks) | en_US |
dc.subject | Particle swarm optimization (PSO) | en_US |
dc.subject | Reverse engineering | en_US |
dc.subject | VLSI circuits | en_US |
dc.subject | Design costs | en_US |
dc.subject | Design space exploration | en_US |
dc.subject | DSP core | en_US |
dc.subject | Functional obfuscation | en_US |
dc.subject | Removal attacks | en_US |
dc.subject | Reverse engineering process | en_US |
dc.subject | Robust locking | en_US |
dc.subject | State-of-the-art approach | en_US |
dc.subject | Locks (fasteners) | en_US |
dc.title | Functional obfuscation of DSP cores using robust logic locking and encryption | en_US |
dc.type | Conference Paper | en_US |
Appears in Collections: | Department of Computer Science and Engineering |
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