Reliability and threat analysis of NBTI stress on DSP cores

Abstract

Device aging is a critical failure mechanism in nanoscale designs. Prolonged device degradation may result in failure. Delay degradation of a design depends on various factors such as threshold voltage, temperature, input vector pattern etc. An attacker who is aware of this phenomenon may exploit by accelerating the performance degradation mechanism. This paper proposes a novel reliability and threat analysis of negative bias temperature instability (NBTI) stress on digital signal processing (DSP) cores. The main contributions of this paper are as follows: (a) identifying input vectors that cause maximum degradation of DSP cores due to NBTI stress (b) analyzing impact of NBTI stress for varying stress time on DSP core in terms of delay degradation (c) analyzing performance comparison of stress vs. no-stress condition for various input vector samples. © 2017 IEEE.