A firefly algorithm driven approach for high level synthesis

Abstract

High Level Synthesis (HLS) for application-specific computer hardware design involves critical decision making steps such as design space exploration (DSE) of resources, scheduling, allocation and binding. Exploring an optimal design solution comprising of array of resource types is a complex problem and requires intelligent decision making in an automated manner. Exploration of an optimal design solution is considered a complex problem as it involves trade-off between contradictory parameters of hardware area and latency amongst numerous candidate design variants. This paper presents the following contributions: (a) novel FA driven DSE methodology during high level synthesis for application specific computing hardware based on area-latency trade-off (b) novel sensitivity analysis that provides optimal tuning of FA control parameters for performing DSE that leads to faster convergence. © 2017 IEEE.