Generating multi-cycle and multiple transient fault resilient design during physically aware high level synthesis

Abstract

Future technologies predict major reliability concern for digital systems due to growing impact of radiation based transient faults. Radiation strikes may produce upsets that last over several clock cycles and that can affect multiple functional units similarly (equivalently). This will be a problem in future as with the evolution of technology, the device geometry continues to shrink massively along with persistent escalation of operating speed. This calls for solutions that can confront the dual problem of multi-cycle and multiple transient faults at higher abstraction level (such as behavioural level) alongside considering lower level physical design information. A novel physically aware high level synthesis (HLS) methodology is presented in this paper, that solves the aforesaid problem by providing resilient designs against transient fault that extend over several control steps (clock cycles) and affect neighborhood functional units similarly, with minimal overhead and implementation runtime. © 2016 IEEE.