Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/4666
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dc.contributor.authorSengupta, Anirbanen_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:35:06Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:35:06Z-
dc.date.issued2016-
dc.identifier.citationSengupta, A., Bhadauria, S., & Mohanty, S. P. (2016). Embedding low cost optimal watermark during high level synthesis for reusable IP core protection. Paper presented at the Proceedings - IEEE International Symposium on Circuits and Systems, , 2016-July 974-977. doi:10.1109/ISCAS.2016.7527405en_US
dc.identifier.isbn9781479953400-
dc.identifier.issn0271-4310-
dc.identifier.otherEID(2-s2.0-84983401487)-
dc.identifier.urihttps://doi.org/10.1109/ISCAS.2016.7527405-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/4666-
dc.description.abstractIntellectual property (IP) cores have emerged as a promising solution to the challenges of future design as well as mounting time to market pressure. However, due to increasing globalization of design supply chain, possibility of intervention and typical attacks is on the rise, which therefore mandates protection of IP cores from piracy/counterfeiting even at behavioral level. This paper presents a technique for generating low cost watermarking solution during high level synthesis (HLS) based on multi-variable signature encoding for security of reusable IP cores. The watermark generated by the proposed approach satisfies the following properties: (a) low embedding cost (b) robustness (c) low watermark creation time (d) strong proof of authorship (e) lower hardware overhead. Comparison with similar technique revealed that proposed approach obtains watermarked solution with lower embedding cost with less storage overhead and creation time. © 2016 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.sourceProceedings - IEEE International Symposium on Circuits and Systemsen_US
dc.subjectCostsen_US
dc.subjectIntegrated circuit designen_US
dc.subjectReconfigurable hardwareen_US
dc.subjectSupply chainsen_US
dc.subjectWatermarkingen_US
dc.subjectBehavioral levelen_US
dc.subjectFuture designsen_US
dc.subjectHardware overheadsen_US
dc.subjectIntellectual property coresen_US
dc.subjectIP securityen_US
dc.subjectMulti variablesen_US
dc.subjectStorage overheaden_US
dc.subjectTime to marketen_US
dc.subjectHigh level synthesisen_US
dc.titleEmbedding low cost optimal watermark during high level synthesis for reusable IP core protectionen_US
dc.typeConference Paperen_US
Appears in Collections:Department of Computer Science and Engineering

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