Rapid search of Pareto fronts using D-logic exploration during multi-objective tradeoff of computation intensive applications

Abstract

Design space exploration in architectural synthesis is a complicated process of balancing multiple orthogonal issues such as a) decreasing the time of exploration as well as enhancing the quality of final solution b) optimizing conflicting objectives such as reducing the power requirement (or alternatively area requirement) as well as augmenting the performance of the final circuit. This paper presents a novel methodology using Dominance criterion (D-logic) to effectively handle the problem of DSE based on either power-execution time tradeoff (with area as an optimization criteria) or area-execution time tradeoff (with power as an optimization criteria). The proposed work introduces novel D-logic mathematical models for three parameters viz. power, execution time and area that deterministically prune the vast design space into a subset of valid design variants without compromising the speed and quality of the design variances. The proposed method is several orders of magnitude faster and superior in terms of searching Pareto fronts and identifying an optimal solution than recent genetic based DSE technique where average improvement in quality of results (QoR) achieved is > 9 % (in terms of power and execution time) and average reduction in exploration time is > 90 %. © 2013 IEEE.