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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Sengupta, Anirban | en_US |
dc.contributor.author | Rathor, Mahendra | en_US |
dc.date.accessioned | 2022-03-17T01:00:00Z | - |
dc.date.accessioned | 2022-03-17T15:35:44Z | - |
dc.date.available | 2022-03-17T01:00:00Z | - |
dc.date.available | 2022-03-17T15:35:44Z | - |
dc.date.issued | 2020 | - |
dc.identifier.citation | Sengupta, A., & Rathor, M. (2020). Obfuscated hardware accelerators for image processing filters - application specific and functionally reconfigurable processors. IEEE Transactions on Consumer Electronics, 66(4), 386-395. doi:10.1109/TCE.2020.3027760 | en_US |
dc.identifier.issn | 0098-3063 | - |
dc.identifier.other | EID(2-s2.0-85091939515) | - |
dc.identifier.uri | https://doi.org/10.1109/TCE.2020.3027760 | - |
dc.identifier.uri | https://dspace.iiti.ac.in/handle/123456789/4849 | - |
dc.description.abstract | Hardware accelerators are widely used as computationally-intensive cores in consumer electronics (CE) applications. However security and speed of such hardware accelerators, that are responsible for computing data-intensive tasks, play an important role in improving consumer experience in terms of safety and performance. This article presents novel low power multi-modal hardware accelerator architectures viz. application specific processor and functionally reconfigurable processor for image processing filter of $3\times 3$ kernel matrix size. In the proposed functionally reconfigurable processor of $3\times 3$ filter, the same design can be used for five different image processing filters - blurring, sharpening, vertical embossment, horizontal embossment and Laplace edge detection, by varying control input. Further, application specific processor designs of these five types of $3\times 3$ filters are also presented in this article. Additionally, application specific processor architecture of $5\times 5$ filter kernel matrix size is also reported in this article. The results confirm that the proposed hardware accelerators achieve strong security and low design cost. © 1975-2011 IEEE. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_US |
dc.source | IEEE Transactions on Consumer Electronics | en_US |
dc.subject | Acceleration | en_US |
dc.subject | Computer hardware | en_US |
dc.subject | Edge detection | en_US |
dc.subject | Hardware security | en_US |
dc.subject | Integrated circuit design | en_US |
dc.subject | Matrix algebra | en_US |
dc.subject | Reconfigurable hardware | en_US |
dc.subject | Application specific | en_US |
dc.subject | Application specific processors | en_US |
dc.subject | Application-specific processor design | en_US |
dc.subject | Hardware accelerator architecture | en_US |
dc.subject | Hardware accelerators | en_US |
dc.subject | Image processing filters | en_US |
dc.subject | Reconfigurable processors | en_US |
dc.subject | Strong securities | en_US |
dc.subject | Image processing | en_US |
dc.title | Obfuscated Hardware Accelerators for Image Processing Filters - Application Specific and Functionally Reconfigurable Processors | en_US |
dc.type | Journal Article | en_US |
Appears in Collections: | Department of Computer Science and Engineering |
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