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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Sengupta, Anirban | en_US |
dc.contributor.author | Kachave, Deepak | en_US |
dc.contributor.author | Roy, Dipanjan | en_US |
dc.date.accessioned | 2022-03-17T01:00:00Z | - |
dc.date.accessioned | 2022-03-17T15:35:59Z | - |
dc.date.available | 2022-03-17T01:00:00Z | - |
dc.date.available | 2022-03-17T15:35:59Z | - |
dc.date.issued | 2019 | - |
dc.identifier.citation | Sengupta, A., Kachave, D., & Roy, D. (2019). Low cost functional obfuscation of reusable IP ores used in CE hardware through robust locking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 38(4), 604-616. doi:10.1109/TCAD.2018.2818720 | en_US |
dc.identifier.issn | 0278-0070 | - |
dc.identifier.other | EID(2-s2.0-85044380340) | - |
dc.identifier.uri | https://doi.org/10.1109/TCAD.2018.2818720 | - |
dc.identifier.uri | https://dspace.iiti.ac.in/handle/123456789/4905 | - |
dc.description.abstract | Intellectual property (IP) cores used in consumer electronics devices mandate protection against reverse engineering (RE) attacks. Functional obfuscation protects the design functionality by enhancing the complexity of RE attacks. This paper proposes a novel low cost (based on power-delay tradeoff) functional obfuscation methodology through employment of robust IP locking technique. In the proposed obfuscation methodology, several strong multipairwise secure IP locking block designs are presented that can only be actuated through application of valid serial key bits. As demonstration, this paper also shows a practical example of a functional obfuscated netlist structure of FIR filter. Proposed obfuscation on comparison with a recent approach for several DSP cores yielded a power reduction of 10%, design cost reduction 6.5% and security enhancement (strength of obfuscation) of > 4.29 e+9 times. © 1982-2012 IEEE. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_US |
dc.source | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | en_US |
dc.subject | Computer hardware | en_US |
dc.subject | Computer software reusability | en_US |
dc.subject | Consumer electronics | en_US |
dc.subject | Cost reduction | en_US |
dc.subject | FIR filters | en_US |
dc.subject | Hardware | en_US |
dc.subject | Hardware security | en_US |
dc.subject | Intellectual property core | en_US |
dc.subject | Internet protocols | en_US |
dc.subject | Locks (fasteners) | en_US |
dc.subject | Logic gates | en_US |
dc.subject | Optimization | en_US |
dc.subject | Reverse engineering | en_US |
dc.subject | Robustness (control systems) | en_US |
dc.subject | Delays | en_US |
dc.subject | Functional Obfuscation | en_US |
dc.subject | IP networks | en_US |
dc.subject | Power-delay tradeoff | en_US |
dc.subject | Security | en_US |
dc.subject | Consumer protection | en_US |
dc.title | Low Cost Functional Obfuscation of Reusable IP Ores Used in CE Hardware Through Robust Locking | en_US |
dc.type | Journal Article | en_US |
Appears in Collections: | Department of Computer Science and Engineering |
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