Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/4909
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dc.contributor.authorKachave, Deepaken_US
dc.contributor.authorSengupta, Anirbanen_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:36:00Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:36:00Z-
dc.date.issued2019-
dc.identifier.citationKachave, D., & Sengupta, A. (2019). Digital processing core performance degradation due to hardware stress attacks. IEEE Potentials, 38(2), 39-45. doi:10.1109/MPOT.2018.2850384en_US
dc.identifier.issn0278-6648-
dc.identifier.otherEID(2-s2.0-85062697117)-
dc.identifier.urihttps://doi.org/10.1109/MPOT.2018.2850384-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/4909-
dc.description.abstractNanoscale designs suffer from a major bottleneck of device aging that is characterized by its failure mechanism. Device aging may be caused by persistent device delay degradation that finally results in failure. Furthermore, some major factors that affect delay degradation are threshold voltage, temperature, and inputvector patterns. This phenomenon of accelerated aging through delay degradation can be easily exploited by a cyberat tacker who has knowledge of it. © 1988-2012 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.sourceIEEE Potentialsen_US
dc.subjectThreshold voltageen_US
dc.subjectAccelerated agingen_US
dc.subjectDevice agingen_US
dc.subjectFailure mechanismen_US
dc.subjectMajor factorsen_US
dc.subjectNano-scale designen_US
dc.subjectProcessing coreen_US
dc.subjectFailure (mechanical)en_US
dc.titleDigital Processing Core Performance Degradation Due to Hardware Stress Attacksen_US
dc.typeJournal Articleen_US
Appears in Collections:Department of Computer Science and Engineering

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