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Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/4911
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dc.contributor.authorRoy, Dipanjanen_US
dc.contributor.authorSengupta, Anirbanen_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:36:00Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:36:00Z-
dc.date.issued2019-
dc.identifier.citationRoy, D., & Sengupta, A. (2019). Multilevel watermark for protecting DSP kernel in CE systems [hardware matters]. IEEE Consumer Electronics Magazine, 8(2), 100-102. doi:10.1109/MCE.2018.2880849en_US
dc.identifier.issn2162-2248-
dc.identifier.otherEID(2-s2.0-85061329996)-
dc.identifier.urihttps://doi.org/10.1109/MCE.2018.2880849-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/4911-
dc.description.abstractThe intellectual property (IP) core for digital signal processors (DSPs) is vulnerable to IP cloning, IP piracy, and ownership abuse. This article presents a hybrid architectural and register-transfer level (RTL) watermark for DSP IP cores to safeguard against these threats. The watermarking constraints are decoded from the owner?s multivariable signature, where each variable indicates an encoded meaning. A case study is presented showing the complete watermarking process for a seventh-order finite impulse response (FIR) filter and its corresponding implementation. © 2012 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.sourceIEEE Consumer Electronics Magazineen_US
dc.subjectDigital signal processorsen_US
dc.subjectFIR filtersen_US
dc.subjectImpulse responseen_US
dc.subjectWatermarkingen_US
dc.subjectCE systemsen_US
dc.subjectIp piraciesen_US
dc.subjectMulti variablesen_US
dc.subjectRegister transfer levelen_US
dc.subjectDigital signal processingen_US
dc.titleMultilevel Watermark for Protecting DSP Kernel in CE Systems [Hardware Matters]en_US
dc.typeJournal Articleen_US
Appears in Collections:Department of Computer Science and Engineering

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