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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Sengupta, Anirban | en_US |
dc.contributor.author | Kachave, Deepak | en_US |
dc.date.accessioned | 2022-03-17T01:00:00Z | - |
dc.date.accessioned | 2022-03-17T15:36:12Z | - |
dc.date.available | 2022-03-17T01:00:00Z | - |
dc.date.available | 2022-03-17T15:36:12Z | - |
dc.date.issued | 2018 | - |
dc.identifier.citation | Sengupta, A., & Kachave, D. (2018). Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesis. Future Generation Computer Systems, 80, 29-46. doi:10.1016/j.future.2017.08.001 | en_US |
dc.identifier.issn | 0167-739X | - |
dc.identifier.other | EID(2-s2.0-85028374265) | - |
dc.identifier.uri | https://doi.org/10.1016/j.future.2017.08.001 | - |
dc.identifier.uri | https://dspace.iiti.ac.in/handle/123456789/4956 | - |
dc.description.abstract | Reusable Intellectual Property (IP) cores have become an obligatory mandate for combating conflicting objectives of maximizing design productivity and minimizing design cycle time. However, a reusable IP core needs protection against false (illegal) claim of ownership. In this paper, we propose a novel computational forensic engineering (CFE) based approach for resolving ownership problem of a reusable IP core generated during high level synthesis (HLS). Some of the major contributions of the proposed approach are as follows: (a) a novel methodology based on multiple design feature set (technology & control parameter independent) that is capable of resolving false claim of vendor ownership problem for an IP core generated during HLS (b) novel algorithms for extracting design features (from register transfer level (RTL) hardware description language (HDL)) of an IP core for determining the rightful owner (c) a novel signature free approach (with avg. runtime ∼2 s) that offers 0% hardware overhead and 0% degradation of IP functionality/quality compared to watermarking based IP ownership resolution techniques. © 2017 Elsevier B.V. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Elsevier B.V. | en_US |
dc.source | Future Generation Computer Systems | en_US |
dc.subject | C (programming language) | en_US |
dc.subject | Computer hardware description languages | en_US |
dc.subject | Design for testability | en_US |
dc.subject | Hardware | en_US |
dc.subject | High level languages | en_US |
dc.subject | High level synthesis | en_US |
dc.subject | Integrated circuit design | en_US |
dc.subject | Intellectual property core | en_US |
dc.subject | Computational forensics | en_US |
dc.subject | Conflicting objectives | en_US |
dc.subject | Control parameters | en_US |
dc.subject | Design productivity | en_US |
dc.subject | Hardware overheads | en_US |
dc.subject | Protection | en_US |
dc.subject | Register transfer level | en_US |
dc.subject | Resolution techniques | en_US |
dc.subject | Forensic engineering | en_US |
dc.title | Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesis | en_US |
dc.type | Journal Article | en_US |
Appears in Collections: | Department of Computer Science and Engineering |
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