Design and Analysis of Ultra-Low Power Memory Architecture with MTCMOS Asymmetrical Ground-Gated 7T SRAM Cell

Abstract

Memory is a basic and essential component for all VLSI systems. As nanoscale complementary metal oxide semiconductor (nano-CMOS) technology is growing, VLSI designers are facing new challenges for fast, low power and high robust memory design. According to the recent trends at nanometer and beyond technology node, noise margins and leakage power dissipation are the challenging parameters for memory cell design engineers. In this paper, an effective MTCMOS asymmetrical SRAM cell is proposed for the designing of memory architecture with least leakage power dissipation and high data stability. Circuit parameters of asymmetrical 7T SRAM cell such as propagation delay, leakage power dissipation and stability are evaluated and compared with ground-gated 6T SRAM cell for designing ultra-low power memory architecture. Pre and post layout simulations of asymmetrical ground-gated 7T (Asym7T) SRAM cell and 4 × 4 memory array architecture are done to get real results. Post layout simulation results are degraded as compared to pre layout simulation results due to inclusion of parasitics. FF corner simulation of Asym7T SRAM cell has delay reduced up to 4.01 × as compared to standard simulation of Asym7T SRAM cell. Asym7T SRAM cell has very less leakage current consumption as compared to standard ground-gated 6T SRAM cell. Asym7T SRAM cell has higher write, read and hold SNM up to 67.45%, 52.18% and 46.56% as compared to ground-gated standard 6T SRAM cell. 4 × 4 memory architecture along with peripheral circuitry such as Asym7T SRAM cells array, decoder and sense amplifiers are designed and simulated. The simulation results are obtained at 1.2 V supply voltage using Cadence EDA tool with 180 nm GPDK technology file. © 2021, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.