Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/5075
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dc.contributor.authorShah, Ambika Prasaden_US
dc.contributor.authorRaut, Gopalen_US
dc.contributor.authorVishvakarma, Santosh Kumaren_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:38:37Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:38:37Z-
dc.date.issued2021-
dc.identifier.citationBeohar, A., Shah, A. P., Yadav, N., Raut, G., & Vishvakarma, S. K. (2021). Design and analysis of cyl GAA-TFET-based cross-coupled voltage doubler circuit doi:10.1007/978-981-16-1570-2_7en_US
dc.identifier.isbn9789811615696-
dc.identifier.issn1876-1100-
dc.identifier.otherEID(2-s2.0-85113709195)-
dc.identifier.urihttps://doi.org/10.1007/978-981-16-1570-2_7-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/5075-
dc.description.abstractIn this work, a cross-coupled voltage doubler based on Cyl GAA-nTFET with improved reliability is proposed for IoT applications. The proposed device is examined and co-design is simulated for circuit behavior for dc/analog characteristics such as ION, IOFF, and sub-threshold swing (SS), and circuit parameters such as power efficiency, output voltage, and energy consumption using 3D TCAD mixed-mode simulation. Further, the proposed circuit nullifies the reverse leakage current due to the arrangement of two non-overlapping clock signals with the tunnel transistors based on hetero-material. The proposed co-design used the merits of low bandgap material like Ge-source region with extreme short width of spacer of 12 nm placed over source, decreases the depletion of the electric field toward the gate, and significantly increases ION. Similarly, structure of underlap in drain increases the depleted electric field effect and significantly increases barrier width toward drain-channel junction to weaken the electric field, consequently lowering IOFF. Moreover, the proposed device is well calibrated and investigates the effects of trap charges while analyzing the TAT model on the device. This co-design approach promotes the power efficiency of up to 95.4% implemented on a 25 nm technology node © 2021, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.en_US
dc.language.isoenen_US
dc.publisherSpringer Science and Business Media Deutschland GmbHen_US
dc.sourceLecture Notes in Electrical Engineeringen_US
dc.subjectCoupled circuitsen_US
dc.subjectElectric field effectsen_US
dc.subjectEnergy utilizationen_US
dc.subjectMicroelectronicsen_US
dc.subjectThreshold voltageen_US
dc.subjectTiming circuitsen_US
dc.subjectTunnel field effect transistorsen_US
dc.subjectChannel junctionsen_US
dc.subjectCircuit behaviorsen_US
dc.subjectCo-design approachen_US
dc.subjectDesign and analysisen_US
dc.subjectMixed mode simulationen_US
dc.subjectReverse leakage currenten_US
dc.subjectSub-threshold swing(ss)en_US
dc.subjectTunnel transistorsen_US
dc.subjectElectric network analysisen_US
dc.titleDesign and Analysis of Cyl GAA-TFET-Based Cross-Coupled Voltage Doubler Circuiten_US
dc.typeConference Paperen_US
Appears in Collections:Department of Electrical Engineering

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