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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Shah, Ambika Prasad | en_US |
dc.contributor.author | Raut, Gopal | en_US |
dc.contributor.author | Vishvakarma, Santosh Kumar | en_US |
dc.date.accessioned | 2022-03-17T01:00:00Z | - |
dc.date.accessioned | 2022-03-17T15:38:37Z | - |
dc.date.available | 2022-03-17T01:00:00Z | - |
dc.date.available | 2022-03-17T15:38:37Z | - |
dc.date.issued | 2021 | - |
dc.identifier.citation | Beohar, A., Shah, A. P., Yadav, N., Raut, G., & Vishvakarma, S. K. (2021). Design and analysis of cyl GAA-TFET-based cross-coupled voltage doubler circuit doi:10.1007/978-981-16-1570-2_7 | en_US |
dc.identifier.isbn | 9789811615696 | - |
dc.identifier.issn | 1876-1100 | - |
dc.identifier.other | EID(2-s2.0-85113709195) | - |
dc.identifier.uri | https://doi.org/10.1007/978-981-16-1570-2_7 | - |
dc.identifier.uri | https://dspace.iiti.ac.in/handle/123456789/5075 | - |
dc.description.abstract | In this work, a cross-coupled voltage doubler based on Cyl GAA-nTFET with improved reliability is proposed for IoT applications. The proposed device is examined and co-design is simulated for circuit behavior for dc/analog characteristics such as ION, IOFF, and sub-threshold swing (SS), and circuit parameters such as power efficiency, output voltage, and energy consumption using 3D TCAD mixed-mode simulation. Further, the proposed circuit nullifies the reverse leakage current due to the arrangement of two non-overlapping clock signals with the tunnel transistors based on hetero-material. The proposed co-design used the merits of low bandgap material like Ge-source region with extreme short width of spacer of 12 nm placed over source, decreases the depletion of the electric field toward the gate, and significantly increases ION. Similarly, structure of underlap in drain increases the depleted electric field effect and significantly increases barrier width toward drain-channel junction to weaken the electric field, consequently lowering IOFF. Moreover, the proposed device is well calibrated and investigates the effects of trap charges while analyzing the TAT model on the device. This co-design approach promotes the power efficiency of up to 95.4% implemented on a 25 nm technology node © 2021, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Springer Science and Business Media Deutschland GmbH | en_US |
dc.source | Lecture Notes in Electrical Engineering | en_US |
dc.subject | Coupled circuits | en_US |
dc.subject | Electric field effects | en_US |
dc.subject | Energy utilization | en_US |
dc.subject | Microelectronics | en_US |
dc.subject | Threshold voltage | en_US |
dc.subject | Timing circuits | en_US |
dc.subject | Tunnel field effect transistors | en_US |
dc.subject | Channel junctions | en_US |
dc.subject | Circuit behaviors | en_US |
dc.subject | Co-design approach | en_US |
dc.subject | Design and analysis | en_US |
dc.subject | Mixed mode simulation | en_US |
dc.subject | Reverse leakage current | en_US |
dc.subject | Sub-threshold swing(ss) | en_US |
dc.subject | Tunnel transistors | en_US |
dc.subject | Electric network analysis | en_US |
dc.title | Design and Analysis of Cyl GAA-TFET-Based Cross-Coupled Voltage Doubler Circuit | en_US |
dc.type | Conference Paper | en_US |
Appears in Collections: | Department of Electrical Engineering |
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