Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/5163
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dc.contributor.authorKranti, Abhinaven_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:38:50Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:38:50Z-
dc.date.issued2019-
dc.identifier.citationGupta, M., & Kranti, A. (2019). Optimization of multiple physical phenomena through a universal metric in junctionless transistors. Paper presented at the Proceedings - 32nd International Conference on VLSI Design, VLSID 2019 - Held Concurrently with 18th International Conference on Embedded Systems, ES 2019, 168-173. doi:10.1109/VLSID.2019.00048en_US
dc.identifier.isbn9781728104096-
dc.identifier.otherEID(2-s2.0-85066890907)-
dc.identifier.urihttps://doi.org/10.1109/VLSID.2019.00048-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/5163-
dc.description.abstractThe work reports on the identification and applicability of a universal metric to suppress gate induced off-state tunneling while preserving impact ionization triggered sub-60 mV/decade current transition and hysteresis in 25 nm Junctionless (JL) MOSFET. At shorter gate length limit, two contrasting physical mechanisms, namely, impact ionization and Band-to-Band Tunneling (BTBT), affect device functionality. Both these phenomenon are analyzed through the evaluation of the product of current density (J) and electric field (E), which defines power generated per unit volume in the device. Hysteresis, in forward and reverse sweeps of applied gate bias, can be accompanied by an undesirable increase in off-current due to BTBT, thus limiting the device performance. The work showcases the relevance of J.E optimization in 25 nm JL device to achieve a subthreshold swing (S) < 5 mV/decade along with a wider hysteresis window ~140 mV at a drain bias (Vds) of 1 V with suppressed off-state tunneling. © 2019 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.sourceProceedings - 32nd International Conference on VLSI Design, VLSID 2019 - Held concurrently with 18th International Conference on Embedded Systems, ES 2019en_US
dc.subjectElectric fieldsen_US
dc.subjectEmbedded systemsen_US
dc.subjectHysteresisen_US
dc.subjectMOSFET devicesen_US
dc.subjectVLSI circuitsen_US
dc.subjectBand to band tunnelingen_US
dc.subjectCurrent transitionsen_US
dc.subjectDevice functionalityen_US
dc.subjectDevice performanceen_US
dc.subjectJunctionlessen_US
dc.subjectJunctionless transistorsen_US
dc.subjectMOS-FETen_US
dc.subjectOff currenten_US
dc.subjectImpact ionizationen_US
dc.titleOptimization of multiple physical phenomena through a universal metric in junctionless transistorsen_US
dc.typeConference Paperen_US
Appears in Collections:Department of Electrical Engineering

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