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Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/5167
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dc.contributor.authorNavlakha, Nupuren_US
dc.contributor.authorKranti, Abhinaven_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:38:51Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:38:51Z-
dc.date.issued2019-
dc.identifier.citationRaza Ansari, M. H., Navlakha, N., Lin, J. -., & Kranti, A. (2019). Architecture evaluation for standalone and embedded 1t-dram. Paper presented at the 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019, doi:10.1109/VLSI-TSA.2019.8804667en_US
dc.identifier.isbn9781728109428-
dc.identifier.otherEID(2-s2.0-85072115978)-
dc.identifier.urihttps://doi.org/10.1109/VLSI-TSA.2019.8804667-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/5167-
dc.description.abstractThis paper analyzes different transistor architectures (inversion mode (IM), accumulation mode (AM) and junctionless (JL)) for standalone as well as embedded DRAM. The performance metrics (retention time (RT), sense margin (SM), current ratio (CR) and write time (WT)) of JL based 1T-DRAM can be improved through stacked JL (SJL) and core-shell (CS) topologies, which separate conduction and storage regions. Results including gate length scalability (25 nm) and high temperature (125 °C) operation indicate the preference for SJL for standalone applications while CS architecture for embedded DRAM. © 2019 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.source2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019en_US
dc.subjectHigh temperature applicationsen_US
dc.subjectVLSI circuitsen_US
dc.subjectAccumulation modesen_US
dc.subjectArchitecture evaluationen_US
dc.subjectHigh temperatureen_US
dc.subjectInversion modesen_US
dc.subjectPerformance metricsen_US
dc.subjectRetention timeen_US
dc.subjectStandalone applicationsen_US
dc.subjectTransistor architectureen_US
dc.subjectDynamic random access storageen_US
dc.titleArchitecture evaluation for standalone and embedded 1t-dramen_US
dc.typeConference Paperen_US
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