1. IDR@IIT Indore
  2. IITI Scholarly Publications
  3. Department of Electrical Engineering
Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/5174
Full metadata record
DC FieldValueLanguage
dc.contributor.authorNavlakha, Nupuren_US
dc.contributor.authorKranti, Abhinaven_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:38:52Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:38:52Z-
dc.date.issued2019-
dc.identifier.citationNavlakha, N., Ansari, M. H. R., Lin, J. -., & Kranti, A. (2019). Performance assessment of TFET architectures as 1T-DRAM. Paper presented at the 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, doi:10.1109/S3S.2018.8640200en_US
dc.identifier.isbn9781538676264-
dc.identifier.otherEID(2-s2.0-85063147720)-
dc.identifier.urihttps://doi.org/10.1109/S3S.2018.8640200-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/5174-
dc.description.abstractAn assessment of Tunnel FET (TFET) architectures for capacitorless dynamic memory applications is presented through composite metrics to balance various trade-offs while regulating hole distribution to determine sense margin, retention time and current ratio. The impact of temperature, bias and scalability on device performance is also investigated. Results highlight the potential of TFET to overcome various trade-offs through optimal architecture, and achieve enhanced composite metrics at sub-100 nm gate lengths. (0) © 2018 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.source2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018en_US
dc.subjectCommerceen_US
dc.subjectEconomic and social effectsen_US
dc.subjectMemory architectureen_US
dc.subjectMicroelectronicsen_US
dc.subjectTunnel field effect transistorsen_US
dc.subject1t dramsen_US
dc.subjectCurrent ratiosen_US
dc.subjectDevice performanceen_US
dc.subjectImpact of temperaturesen_US
dc.subjectOptimal architectureen_US
dc.subjectPerformance assessmenten_US
dc.subjectRetention timeen_US
dc.subjectTFETen_US
dc.subjectDynamic random access storageen_US
dc.titlePerformance assessment of TFET architectures as 1T-DRAMen_US
dc.typeConference Paperen_US
Appears in Collections:Department of Electrical Engineering

Files in This Item:
There are no files associated with this item.
Show simple item record


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

Altmetric Badge: