1T DRAM with vertically stacked n-oxide-p architecture

Abstract

In this work, vertically stackedn-oxide-p transistor architecture is explored as 1T-DRAM. The moderately dopedp type region is utilized to modulate (i) state currents flowing through the top n-type conduction region, and (ii) Retention Time (RT) through charges stored at the back surface of p-type storage region. The creation of deeper potential well for charge storage inp-region is based on electrostatic doping effect (underneath Source/Drain regions and high gate workfunction values). ART of ∼1 s and ∼1 ms at gate lengths of 200 nm and 25 nm, respectively, at 85°C can be achieved. A low-κ (SiO2) material for the separation of conduction and storage regions enables a higher RT due to lower electric field in the storage region. © 2018 IEEE.