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Please use this identifier to cite or link to this item: https://dspace.iiti.ac.in/handle/123456789/5269
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dc.contributor.authorNavlakha, Nupuren_US
dc.contributor.authorKranti, Abhinaven_US
dc.date.accessioned2022-03-17T01:00:00Z-
dc.date.accessioned2022-03-17T15:39:11Z-
dc.date.available2022-03-17T01:00:00Z-
dc.date.available2022-03-17T15:39:11Z-
dc.date.issued2017-
dc.identifier.citationNavlakha, N., Lin, J. -., & Kranti, A. (2017). Design optimization of tunnel FET for dynamic memory applications. Paper presented at the EDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuits, , 2017-January 1-2. doi:10.1109/EDSSC.2017.8126454en_US
dc.identifier.isbn9781538629079-
dc.identifier.otherEID(2-s2.0-85043582650)-
dc.identifier.urihttps://doi.org/10.1109/EDSSC.2017.8126454-
dc.identifier.urihttps://dspace.iiti.ac.in/handle/123456789/5269-
dc.description.abstractThe work reports on an innovative design to improve the scalability of misaligned Double Gate (DG) Tunnel Field Effect Transistor (TFET) for operation as dynamic memory. The design optimization is achieved through use of lateral gap on both edges of back gate (G2) that reduces Band-To-Band Tunneling (BTBT) and enhances Retention Time (RT) by a factor of -3. The front gate responsible for read mechanism can be scaled down to 75 nm while G2 can be scaled until 40 nm. The investigation highlights better scalability and improved retention characteristics. © 2017 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.sourceEDSSC 2017 - 13th IEEE International Conference on Electron Devices and Solid-State Circuitsen_US
dc.subjectDynamic random access storageen_US
dc.subjectElectron devicesen_US
dc.subjectElectron tunnelingen_US
dc.subjectMOS devicesen_US
dc.subjectScalabilityen_US
dc.subjectSolid state devicesen_US
dc.subjectTunnel field effect transistorsen_US
dc.subjectBand to band tunnelingen_US
dc.subjectDesign optimizationen_US
dc.subjectDouble gateen_US
dc.subjectDynamic memoryen_US
dc.subjectInnovative designen_US
dc.subjectRetention characteristicsen_US
dc.subjectRetention timeen_US
dc.subjectTunnel field-effect transistors (TFET)en_US
dc.subjectField effect transistorsen_US
dc.titleDesign optimization of tunnel FET for dynamic memory applicationsen_US
dc.typeConference Paperen_US
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