Optimization of back gate workfunction, alignment and bias for charge retention in TFET based DRAM

Abstract

The present work reports on design optimization of Tunnel Field Effect Transistor (TFET) in Silicon-on-Insulator (SOI) technology to function as dynamic memory with improved retention characteristics. The front gate of TFET is aligned at a partial portion of intrinsic region and primarily controls the read mechanism based on band-to-band tunneling (BTBT) while the back gate creates a physical well for charge storage. The back gate workfunction and alignment is crucial for the formation of a deep potential well that can sustain charges for longer duration. The optimized bias values on incorporation with appropriate workfunction and position of back gate, aid to charge preservation in the physical well and, hence result into enhanced retention characteristics. Through a systematic approach, retention time of 170 ms at 85 °C for Ultra Thin Buried Oxide (UTBOX) TFET is achieved which is a significant improvement over previous work on TFET based dynamic memory. © 2016 IEEE.