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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kranti, Abhinav | en_US |
dc.date.accessioned | 2022-03-17T01:00:00Z | - |
dc.date.accessioned | 2022-03-17T15:39:16Z | - |
dc.date.available | 2022-03-17T01:00:00Z | - |
dc.date.available | 2022-03-17T15:39:16Z | - |
dc.date.issued | 2017 | - |
dc.identifier.citation | Yu, C. -., Lin, J. T., Chang, T. -., Lin, C. -., Haung, C. -., & Kranti, A. (2017). A vertical and junctionless channel with T-shaped gate 1T-DRAM using new operate mechanism. Paper presented at the 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings, 863-865. doi:10.1109/ICSICT.2016.7999063 | en_US |
dc.identifier.isbn | 9781467397179 | - |
dc.identifier.other | EID(2-s2.0-85028648618) | - |
dc.identifier.uri | https://doi.org/10.1109/ICSICT.2016.7999063 | - |
dc.identifier.uri | https://dspace.iiti.ac.in/handle/123456789/5295 | - |
dc.description.abstract | A vertical junctionless channel with T-shaped gate (VJCT) structure has been proposed as 1T DRAM. Designing in vertical channel topology can overcome scalability issues and reduce the area occupied. Also, the junctionless architecture of the channel can be easily fabricated. The T-shaped gate enhances the gate controllability over the channel and improves performance. Therefore, the proposed structure can enhance programming window and retention time. In addition, we use a new operating mechanism to achieve high writing speed and low power consumption for the device. © 2016 IEEE. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_US |
dc.source | 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings | en_US |
dc.subject | Low-power consumption | en_US |
dc.subject | Operating mechanism | en_US |
dc.subject | Programming window | en_US |
dc.subject | Retention time | en_US |
dc.subject | Scalability issue | en_US |
dc.subject | T-shaped gate | en_US |
dc.subject | Vertical channels | en_US |
dc.subject | Writing speed | en_US |
dc.subject | Integrated circuits | en_US |
dc.title | A vertical and junctionless channel with T-shaped gate 1T-DRAM using new operate mechanism | en_US |
dc.type | Conference Paper | en_US |
Appears in Collections: | Department of Electrical Engineering |
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