A New Sense Amplifier Design with Improved Input Referred Offset Characteristics for Energy-Efficient SRAM

Abstract

For SRAM sense amplifiers (SAs), higher offset voltages lead to an increased likelihood of an incorrect decision. Because differential SA is vulnerable to the bias current offset in the differential legs. Thus, SRAM suffer from slow read speed or low read yield. This paper for the first time presents a novel differential-current-compensation based SA (DCC-SA) to suppress the effect of offset due to device mismatch on SA differential current. The proposed scheme is rigorously analyzed and compared to the conventional schemes. The proposed technique, enable DCC-SA to achieve 0.66× and 0.86× tighter offset distribution than conventional current latch SA (CLSA) and SA with offset compensation (SAOC) respectively, under similar cell current and bitline capacitance. We design a CMOS-logic-compatible, 65 nm, 4 Kb SRAM macro, using the DCC-SA. This technique possesses up to 31%, 55%, 35% and 69% lower energy/access and 0.58×,-1.27×, 0.53× and 0.41× lower resolution time (RT), compared to CLSA, SAOC, Schmitt Trigger (ST) based SA (STn-SA), and stacked SA (STk-SA) respectively at worst case process corners. Further, the standard deviation (σ) of delay for DCC-SA is reduced to 0.3× and 0.56×, 0.3× and 0.54× as that of CLSA, SAOC, STn-SA and STk-SA respectively. © 2016 IEEE.