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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Vishvakarma, Santosh Kumar | en_US |
dc.date.accessioned | 2022-03-17T01:00:00Z | - |
dc.date.accessioned | 2022-03-17T15:41:31Z | - |
dc.date.available | 2022-03-17T01:00:00Z | - |
dc.date.available | 2022-03-17T15:41:31Z | - |
dc.date.issued | 2017 | - |
dc.identifier.citation | Yadav, N., Beohar, A., & Vishvakarma, S. K. (2017). Analysis of single-trap-induced random telegraph noise on asymmetric high-k spacer FinFET. Paper presented at the Proceedings - 2016 IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2016, 264-267. doi:10.1109/iNIS.2016.067 | en_US |
dc.identifier.isbn | 9781509061693 | - |
dc.identifier.other | EID(2-s2.0-85013772539) | - |
dc.identifier.uri | https://doi.org/10.1109/iNIS.2016.067 | - |
dc.identifier.uri | https://dspace.iiti.ac.in/handle/123456789/5320 | - |
dc.description.abstract | In this paper, we analyze the effects of single-chargetrapinduced random telegraphic noise (RTN) on asymmetricdual high-K spacer based FinFET (ADS-FinFET). The effectsof RTN reduces in proposed device because asymmetric high-K spacer reduces the electric field effect at source and formation of the barrier between source to gate/drain. The spacer width optimization will provide maximum possible performance and tolerant towards RTN at 12 nm high-K spacer width. Reduced equivalent oxide thickness (EOT) also help to reduce RTN effect whereas, RTN impact increases with device scaling. © 2016 IEEE. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_US |
dc.source | Proceedings - 2016 IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2016 | en_US |
dc.subject | Electric field effects | en_US |
dc.subject | Electric fields | en_US |
dc.subject | Information systems | en_US |
dc.subject | Nanoelectronics | en_US |
dc.subject | Processing | en_US |
dc.subject | Reliability | en_US |
dc.subject | Asymmetric Spacer | en_US |
dc.subject | Dual spacer | en_US |
dc.subject | High- k | en_US |
dc.subject | Scaling | en_US |
dc.subject | Variation | en_US |
dc.subject | FinFET | en_US |
dc.title | Analysis of single-trap-induced random telegraph noise on asymmetric high-k spacer FinFET | en_US |
dc.type | Conference Paper | en_US |
Appears in Collections: | Department of Electrical Engineering |
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