Rtl level implementation of high speed-low power viterbi encoder & decoder

Abstract

High speed and low power Viterbi Encoder Decoder of rate convolutional coding with a constraint length K = 3 is presented in this paper. After implementation of proposed Viterbi encoder-decoder in Virtex 7 Field Programmable Gate Array (FPGA) kit we come to know that it's functioning on 393.544 MHz clock and in such a high speed it also maintain a low power of 11.34 mW in Spartan 6 FPGA. Since the FPGA boards used are different and from that we justified that using both logics together in one Integrated Circuit (IC) we can create a high speed and low power Viterbi encoder decoder at the same time with some extra hardware area. High speed and low power Viterbi Encoder Decoder of rate convolutional coding with a constraint length K = 3 is presented in this paper. After implementation of proposed Viterbi encoder-decoder in Virtex 7 Field Programmable Gate Array (FPGA) kit we come to know that it's functioning on 393.544 MHz clock and in such a high speed it also maintain a low power of 11.34 mW in Spartan 6 FPGA. Since the FPGA boards used are different and from that we justified that using both logics together in one Integrated Circuit (IC) we can create a high speed and low power Viterbi encoder decoder at the same time with some extra hardware area. © 2013 IEEE.